![]() If the test clock runs faster than 16 times, the 16-bit counter will wrap around and the frequency we detect the wrong frequency. In the VHDL code for clock counter, the reference counter is set to 12 bit and the test counter is 16 bit: the test clock can run up to 16 times (16-12 bit: 2^4 = 16) faster than the reference clock. In the VHDL code, the r1_ and r2_ prefixes denote the referenceand test clock domain respectively.Īs clear the “ p_clock_test_resync” process resynchronize the control signal versus the test clock domain, and this guarantee the layout tool to work fine in the test clock domain. O_clock_freq <= std_logic_vector(r2_counter_test) R2_counter_test '1') - set all bit to '1' at reset and if test clock is not present P_counter_ref : process (i_rstb,i_clk_ref) Signal r2_counter_test_strobe : std_logic Signal r2_counter_test : unsigned(15 downto 0) - clock test can be up-to 16 times clock ref Signal r1_counter_test_strobe : std_logic Signal r1_counter_ref : unsigned(12 downto 0) - 12+1 bit: extra bit used for test counter control r1_ register con clock reference domain O_clock_freq : out std_logic_vector(15 downto 0)) Īrchitecture rtl of clock_freq_counter is If you do not perform such re-synchronization the layout tool could implement the correct control logic for the clock test domain. In the Figure2, it is clear that the control signal for the test counter is resynchronized in the test clock domain in order to control the counter test. When we have to handle two different asynchronous clock domain we need to pay attention in clock domain crossing (CDC) The test clock frequency will be: 2048/4096* 50 = 0.5 * 50 = 25 MHz (40 ns)Īs in simulation reported in Figure4 Figure4 – VHDL code clock counter simulation with test clock 25 MHz VHDL code for the clock frequency counterĪs we saw, the basic idea in clock frequency computing is very simple, but we have to pay attention in implementing the VHDL component.Īs you can see the two clock, reference clock, and test clock, are asynchronous. So we can use the reference clock counter to start and stop the clock test counter.Įvery 2^12 reference clock counting the test clock counts for 10240 as in simulation reported in Figure3ġ0240/4096* 50 MHz = 2.5*50 = 125 MHz (8 ns) Figure3 – VHDL code clock counter simulation with test clock 125 MHzĪ second example, if test clock counter counts for 2048 In order to compute the test clock frequency, we need to know how many clock cycles of the test clock are present into the reference interval. ![]() 20 ns, the counting value is 2^12, counting time period is: For instances if the test clock is 50 MHz, i.e. The reference clock counts for a fixed number clock cycles. The basic idea is reported in the figure Figure2 – Clock counter architectureĪs you can see, we use a reference clock to detect a test clock. So let’s see how to implement a clock frequency counter. The first solution maybe didn’t need a blog post or further explanation If we need to verify the clock frequency, we can How can you measure the clock frequency? You can guess something from the blinking rate but is only a rough estimation.Ĭlick Here to enroll the free course “How To Measure Clock Frequency in FPGA” Doing this you can monitor if your clock is present. I mean, connect the clock to a module that implements a counter to generate a slow signal that can drive a LED for instance at the toggling rate of one second. if you divide the clock rate to a “human” frequency you can use it to blink a LED. The clock is a periodic signal changing very fast, so you cannot directly connect to a LED but…. Well, if you did simulate your VHDL design, and you did respect the golden rules for a digital design ( you can find some example and the available courses here) external reset and clock are often the main issues of your design!įor the reset pin, the solution is very simple: you can map reset to an output pin connected to a LED so you can check if the reset signal is working fine… Maybe you are thinking… it is not possible that the main errors are the clock and reset!
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